Annapurna Labs, part of Amazon, seeks an ASIC Physical Design Engineer in Cupertino to drive floorplanning, placement, integration, and tapeout for advanced SoCs. You will collaborate with the FE team to translate RTL into robust physical designs, and lead DV/verification using Calibre, IC Validator and PVS across processes.
The role requires 5+ years in physical verification, scripting, and strong communication. Experience with FC/Innovus flows and mentoring is preferred.
#J-18808-LjbffrSenior ASIC Physical Design Engineer – Top-Level in cupertino at Unknown Company
This position is listed as full time and onsite.