Senior ASIC Physical Design Engineer – RTL to GDSII

Tektronix is seeking an experienced ASIC Physical Design Engineer to join one of its design centers in Louisville, CO or Beaverton, Oregon. You will drive floorplanning, placement, clock-tree synthesis, routing, and timing closure for SOCs.

Collaborate with RTL, verification, DFT, and packaging teams to deliver tapeout-ready designs. Strong scripting skills and Cadence/Synopsys/Siemens tools are required.