MatX Inc. in Mountain View, CA, is seeking silicon physical design engineers to develop high-performance, power-efficient silicon for GenAI. You will own subsystems and drive PD from RTL to tapeout, ensuring scalable, correct implementations.
The role requires BS in Electrical Engineering and 8+ years of ASIC PD experience, with strong Python/TCL/Perl skills and collaboration with Design/DFT teams to optimize performance, power, and area.
#J-18808-LjbffrSenior ASIC Physical Design Engineer – PPA & Tapeout in mountain view at Unknown Company
This position is listed as full time and onsite.