Senior ASIC Physical Design Engineer

Johns Hopkins Applied Physics Laboratory (APL) seeks a Senior ASIC Physical Design Engineer to lead RTL-to-GDSII implementation for cutting-edge national security, space, and health missions. You will own floorplanning, place-and-route, timing closure, and signoff for advanced-node ASICs and SoCs, collaborating with RTL, verification, and architecture teams. You’ll guide EDA flow development, drive power and reliability optimization, and mentor junior engineers, all within APL’s mission-driven, collaborative, and research-focused culture that supports innovation, advanced study, and career growth.