Google Inc. is seeking a Mid-level Physical Design Engineer in Mountain View, CA to drive ASIC RTL2GDS implementation with focus on high performance, power, and area. You will work with cross-functional teams to deliver top-tier silicon features and optimizations for Google's products.
The role requires a Bachelor's in Electrical Engineering, 4 years in physical design, and hands-on experience with synthesis/PnR flows. Strong Verilog/SystemVerilog and scripting skills are highly valued.
#J-18808-LjbffrSenior ASIC Physical Design Engineer, Full-Chip in mountain view at Unknown Company
This position is listed as full time and onsite.