ACL Digital is seeking a Physical Design Engineer in Austin, Texas with over 6 years of ASIC physical design experience to drive block-level and full-chip implementations. The role requires expertise in handling activities from RTL to GDSII for advanced technology nodes. Responsibilities include performing floorplanning, power planning, and timing closure, while collaborating with verification teams. Strong experience with Cadence Innovus or Synopsys ICC2, along with scripting skills, is essential for the position.
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