Google is seeking a Senior ASIC Engineer in Mountain View to lead the RTL2GDS flow for high-performance, power-efficient ASICs. You will drive full-chip physical implementation and partner with cross-functional teams to deliver cutting-edge silicon solutions.
Ideal candidates have a strong background in physical design, high-performance PnR, STA optimizations, and a deep understanding of ASIC design flows. Join a team shaping the future of hardware experiences at Google.
#J-18808-LjbffrSenior ASIC Physical Design Eng - Full-Chip PPA, Equity in mountain view at Unknown Company
This position is listed as full time and onsite.