Senior ASIC PD Methodology Engineer

Annapurna Labs (U.S.) Inc. in Austin, TX is seeking an ASIC Physical Design Methodology Engineer to shape the design and verification flows for ML accelerator chips in advanced nodes.

You will work across RTL, Physical Design, and CAD teams to drive innovations and ensure high design quality in a cloud-scale environment. Join a team responsible for AWS Inferentia and Trainium systems, collaborating with EDA vendors, building scalable flows, and delivering robust, power-aware hardware solutions