NVIDIA is seeking a Senior ASIC Physical Design Engineer to join the Cache Coherent Interconnects team in Santa Clara, CA. You will drive the physical design of the on-chip interconnects and last-level caches, focusing on synthesis, timing closure, and power/area goals while coordinating with the RTL and logic teams.
The role requires a Master's degree and 5+ years in high-performance semiconductor design, with strong Verilog, PD tools, and RTL/DFT/ECO expertise.
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