Senior ASIC PD Engineer — Cache Coherent Interconnects

NVIDIA is seeking engineers for the CPU Cache Coherent Interconnects Design Team to drive physical design of the on-chip interconnect network and last-level caches, with responsibilities across synthesis, timing closure, and collaboration with logic teams on micro-architecture feasibility.

The role requires a Master’s degree and 5+ years in high-performance semiconductor design, with strong Verilog expertise and experience in RTL, DFT, and ECO.