NVIDIA Corporation in Santa Clara, CA, seeks a Senior ASIC Physical Design Engineer, Netlisting to drive high-frequency, low-power chip design at block/full-chip level, focusing on netlist checks, timing convergence and ECO implementation.
BS +5y or MS +3y in EE/CE, strong RTL/logic design, clock-domain crossing, STA, and scripting (Python/TCL/Perl) required; experience with industry EDA tools and debugging highly valued. Hybrid work option.
#J-18808-LjbffrSenior ASIC Netlisting & Physical Design Engineer - Hybrid in santa clara at Unknown Company
This position is listed as full time and hybrid.