Senior ASIC/FPGA Verification Lead (SystemVerilog/UVM)

Prattwhitney is seeking a Principal Electrical or Computer Engineer in Cedar Rapids, Iowa, to lead the design, implementation, and verification of advanced testbenches for high-performance digital ASICs and FPGAs. Candidates should have at least 8 years of relevant experience and strong knowledge of RTL development using VHDL or SystemVerilog.

This role offers a competitive benefits package that includes medical insurance, 401(k) matching, tuition reimbursement, and various wellness programs.