Senior ASIC/FPGA Design Engineer - RTL to GDS

Advanced Micro Devices, Inc. in San Jose, CA is seeking a hardware design engineer to contribute to FPGA product development within the AECG group.

You will participate in RTL development, implement complex digital and mixed-signal blocks, and collaborate with cross-functional teams across time zones to deliver silicon and software solutions. The role requires strong Verilog/SystemVerilog RTL experience, proficiency with UVM-based verification, and scripting in Python/Perl/Tcl/Shell.