A leading technology company in California is seeking an experienced ASIC Design Verification Engineer to oversee the verification lifecycle for digital power IPs. The ideal candidate will have at least 3 years of experience in verification roles and a Bachelor's degree or higher in related fields. This position offers a competitive salary range of $153,200.00 - $229,800.00 with additional benefits including a discretionary bonus program.
#J-18808-Ljbffr
#J-18808-Ljbffr
Senior ASIC DV Engineer — Tapeouts, UVM & Power in santa clara at Unknown Company
This position is listed as full time and onsite.