Senior Asic Digital Design EngineerWe're looking for an advanced Asic design engineer with solid hands-on experience in RTL design and a foundational understanding of the full Asic/FPGA design lifecycle. This is a technical role for someone who is ready to take on meaningful ownership of design tasks within a collaborative, high-performing team.If your career has been primarily running P&R tools, this probably isn't the right fit. We also need someone who has moved beyond the "burn it and see if it works" model of FPGA development on Asic, you don't get that luxury. We need an RTL designer who understands that correctness has to be established through rigorous simulation, formal verification, and independent review long before anything gets near silicon.The right candidate has worked in larger, structured design environments where verification is a discipline in its own right with dedicated verification partners, formal review processes, and clear functional closure criteria.
A self-starter who can work independently on assigned tasks, drives progress without constant direction, and brings a problem-solving mindset to everything they touch.What You'll DoOwn RTL design tasks Develop RTL with a focus on correctness: bus fabric integrity, clock domain crossings, reset order-of-operations, and design-for-verificationContribute to timing closure Work through synthesis, place and route, and static timing analysis; identify root causes of timing failures and contribute to fixesSupport verification efforts Execute test and simulation plans in coordination with a dedicated verification team; understand and work within a formal verification process; verify results and help drive closure on failuresParticipate in JIRA triage Review incoming issues and help maintain an accurate and actionable backlogParticipate in code reviews Engage in RTL code reviews, providing and receiving constructive technical feedbackSupport program planning Provide input on task status, schedule risk, and level of effort to support IMS and EV reportingSupport proposals Contribute to basis of estimates (BOEs) for proposals, providing technical input on scope and level of effort for assigned design tasksSupport technology evaluation Assist in assessing foundry technologies, device libraries, IP cores, and EDA toolingCollaborate broadly Participate in Integrated Product Teams and working groupsWhat We're Looking For58+ years of Asic/FPGA design experience, with meaningful time spent as an RTL designerExperience working in larger, structured design teams with formal verification processes and independent verification partners not solely in small-team or solo development environmentsDemonstrated understanding that design correctness is established through simulation, formal verification, and peer review not through iteration on hardwareSome experience contributing to Asic tape-out efforts is a plusFamiliarity with FinFET process nodes (7nm, 5nm, or similar) is a differentiatorFamiliarity with commercial foundry flows (TSMC, GlobalFoundries, Samsung, or equivalent)Working knowledge of:RTL design and microarchitectureBus fabric design and verificationClock domain crossing (CDC) analysisReset sequencing and validationTiming closure fundamentalsPower analysis basicsSkills & KnowledgeSolid understanding of Asic/FPGA engineering concepts, RTL coding practices, and synthesis flowsFamiliarity with industry-standard EDA tools (synthesis, simulation, formal verification, STA)Ability to work independently on assigned tasks while coordinating effectively within the teamFamiliarity with vendor and foundry capabilitiesProficiency in JIRA for issue tracking and backlog managementProficiency in Microsoft Office for documentation and communicationWhy This RoleYou won't be handed a spec and told to code. You'll take real ownership of design tasks, with exposure across the full Asic lifecycle and the opportunity to grow alongside experienced engineers. This is a role where your work matters, your initiative is recognized, and the team values engineers who take ownership and see problems through to resolution.Salary Note This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary.
This job posting will remain open until the position is filled. Combined Salary Range USD $142,166.00 - USD $150,000.00 /Yr.Company OverviewGeneral Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency.
We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans