Senior ASIC DFT Tech Lead – Post-Silicon Validation

Cisco Systems, Inc. in San Jose, CA seeks an ASIC Technical Lead focused on Design-for-Test. You will collaborate with Front-end RTL and backend physical design teams to drive DFT requirements early in the design cycle and lead the post-silicon validation efforts for next-generation networking chips.

Ideal candidate has 12+ years in ASIC/DFT, with experience in JTAG, BIST, ATPG, and EDA tools like TestMax, Tetramax, Tessent, and PrimeTime. Strong debugging skills with VCS are essential.