Cisco Systems, Inc. is seeking an ASIC DFT STA Engineer in San Jose, California. This role involves collaborating with teams to develop and validate timing constraints, driving the DFT process through implementation.
Ideal candidates should possess a strong background in timing constraints, FPGA design, and scripting. The position offers a competitive salary range between $165,000 to $241,400 annually, reflecting the value of skilled professionals in today’s AI-driven tech environment.
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