Google is seeking a Senior ASIC DFT Engineer, Silicon, to lead DFT architecture across SoCs, collaborating with RTL, Physical Design, and Product teams.
The role requires 8+ years in DFT, experience with Tessent, Genus, Fusion Compiler, Simvision, and scripting in Python or Perl to automate flows. You will drive scan implementation, MBIST, ATPG, and IJTAG tooling.
This is a hands-on role with end-to-end DFT from architecture to silicon debug within Google's innovative hardware team.
#J-18808-LjbffrSenior ASIC DFT Engineer: Lead Subsystem DFT & Debug in mountain view at Unknown Company
This position is listed as full time and onsite.