Senior ASIC DFT Architect - Hybrid Work & SoC IP

NVIDIA is seeking a Senior ASIC Design Engineer to join the DFT team in Santa Clara. You will own fuse controller and DFT IP design for cutting-edge SoCs, while advancing scalable DFT methods and collaborating across architecture, design, and verification groups.

You will partner with multiple teams to define features, validate through test plans, and support post-silicon bring-up. A strong Verilog background and UVM familiarity are valued assets.