Senior ASIC Design Engineer — SoC Power & IP

Apple seeks an ASIC Design Engineer in Cupertino, CA to architect power management for the SoC and to write specifications for IPs. You will design, implement, and debug complex logic and integrate IPs into the SOC, while coordinating with front end teams and software groups.

The role requires a BS with 10+ years in the industry, experience leading a team of logic designers, and strong knowledge of clock domains, system architecture, and power/clock management designs.