Google is seeking a hardware architect to define microarchitecture for silicon subsystems and integrate IP blocks to meet performance, area, and power goals. You will code RTL, debug complex simulations, and verify designs with lint, clock-domain crossing, and formal checks.
Collaboration with validation teams ensures thorough coverage and timely delivery. Ideal candidates have a strong background in ASIC design methodologies, clock domain checks, and low-power design, with experience in
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