SpaceX is seeking a Senior ASIC Design Engineer to contribute to the Silicon Engineering team and develop next-generation ASICs for Starlink hardware. The role focuses on RTL implementation, verification, and timing closure, with collaboration across verification and physical design teams.
The ideal candidate has 5+ years of RTL experience and a strong background in high-speed, low-power ASIC design, earning opportunities tied to cutting-edge space infrastructure projects.
#J-18808-LjbffrSenior ASIC Design Engineer - RTL & SoC for Space Systems in irvine at Unknown Company
This position is listed as full time and onsite.