Celero Communications is seeking an ASIC Design Engineer to develop high-speed digital ASICs for optical communications and data center infrastructure. You will lead RTL design, verification, and integration with DSP, SerDes, and mixed-signal blocks.
The role requires strong Verilog/SystemVerilog expertise, 5+ years in digital ASIC design, and collaboration across multiple engineering teams in a fast-paced startup environment. Competitive US base salary is offered.
#J-18808-LjbffrSenior ASIC Design Engineer - Optical & High-Speed DSP in san jose at Unknown Company
This position is listed as full time and onsite.