Senior ASIC Design Engineer - ML Inference Acceleration

Annapurna Labs, an AWS subsidiary, is seeking an ASIC Design Engineer in Cupertino to design high-performance RTL for SOCs and integrate subsystems. You will work with cross‑functional teams across architecture, verification, and back‑end to meet power, area and timing targets.

The role requires a strong background in RTL design, SystemVerilog, and VLSI, plus hands-on scripting in Python. We value collaboration, mentoring, and a passion for hardware innovation.