Amazon is seeking an ASIC Design Engineer in Austin, TX to design and optimize hardware for AWS ML servers. You will develop RTL in SystemVerilog, run timing and lint checks, and collaborate with cross-functional teams to balance performance, area, and power while ensuring design quality.
The ideal candidate has a strong ASIC design background, SystemVerilog expertise, and a proven ability to debug complex architectures. A Bachelor’s in EE is required; advanced degrees are preferred.
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