Senior ASIC Design Engineer - Low-Power SOC & WiFi

Qualcomm Atheros, Inc. in Santa Clara, CA seeks an experienced ASIC Design Engineer to develop low-power micro-architecture for WiFi SOCs, spanning from specs to post-silicon bring-up. You will drive the design through RTL, verification, timing, and power analysis.

You will collaborate with the verification team to craft verification plans, perform silicon power measurements, and lead silicon bring-up and debug activities across multi-domain clocking and AMBA protocols.