Senior ASIC Design Engineer — Low-Latency ML Compute

Selby Jennings is seeking an experienced ASIC Design Engineer to join its Hardware Engineering team in New York. You will architect and implement high‑performance digital designs for latency‑sensitive applications, collaborating with ML researchers, software engineers, and quantitative researchers to optimize silicon.

The role requires 5+ years in ASIC design, strong SystemVerilog/RTL skills, and a deep understanding of computer architecture and ASIC flows.