Senior ASIC Design Engineer - High-Speed Optical DSP

Celero Communications, Inc. in Irvine, CA seeks an experienced ASIC Design Engineer to develop high-speed digital blocks for optical communication systems. You will lead RTL design, Verilog/SystemVerilog, and work with DSP, SerDes, and mixed-signal teams from architecture through silicon bring-up.

The role emphasizes performance, power, and area optimization, synthesis and verification using industry-standard EDA tools, and scripting in Python or Tcl to automate flows. A Master’s or Ph.D.