Micron Technology in San Jose, California, seeks a Senior ASIC Design Engineer to own the full ASIC lifecycle—from specs and microarchitecture to design, synthesis, timing, linting and CDC, leveraging GenAI to boost efficiency.
Requirements include 5+ years in ASIC design, a B.S. in EE or CS, proficiency with SystemVerilog and EDA flows, knowledge of PCIe/NVMe and memory interfaces. A Master’s degree and experience with DFT/CDC are a plus.
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