A pioneering technology company located in San Jose is seeking an experienced ASIC Sr. Staff Engineer to design and debug complex digital subsystems. The ideal candidate should have a strong background in digital design, specifically with Verilog and SystemVerilog, along with expertise in ASIC verification. This role involves collaborative development of algorithm specifications and hands-on work with high-speed optical systems. Competitive salary range from $180,000 to $223,000 is offered, while promoting a diverse and inclusive workplace.
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