Senior ASIC Design Engineer AI Networking & SoC

Advanced Micro Devices in Santa Clara, CA is seeking a Senior ASIC Design Engineer to lead high‑speed ASIC development from RTL architecture through tapeout and production. You will work across ASIC lifecycle with cross‑functional teams to deliver optimized networking and data‑movement blocks.

The role emphasizes collaboration, debug across multiple stages, and documentation. A strong background in Verilog/SystemVerilog, C/C++, Python, and networking is required.