Senior ASIC Design Engineer – AI Accelerator / SoC

Xscend is looking for a Senior ASIC Design Engineer to lead the architecture, microarchitecture, and RTL development for next-generation AI accelerators and high-performance SoC subsystems. The role requires extensive hands-on experience in digital ASIC design, particularly with GPU, NPU, or complex SoC architectures, and involves optimizing designs for performance, power, and area throughout the ASIC development lifecycle.

Responsibilities

• Develop detailed microarchitecture specifications based on system-level and functional requirements.
• Design and implement complex digital logic using Verilog/SystemVerilog.
• Create high-performance datapaths, control logic, finite state machines, and communication interfaces.
• Optimize RTL designs for timing, power consumption, and silicon area.
• Conduct RTL code reviews and functional debugging.
• Collaborate with architecture engineers to evaluate design trade-offs.
• Design functional blocks for AI accelerators and complex SoC architectures.
• Develop compute pipelines, memory interfaces, and data movement logic.
• Integrate memory controllers and high-speed interface subsystems.
• Support ASIC development from specification to tape-out, ensuring production-quality RTL.
• Collaborate with verification engineers to develop functional verification plans and test scenarios.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 5 years of hands-on experience in digital ASIC/SoC design and RTL implementation.
• Strong knowledge of GPU, NPU, or complex SoC architectures.
• Proficiency in Verilog/SystemVerilog RTL design.
• Experience in translating functional specifications into microarchitecture and synthesizable RTL.
• Solid understanding of digital logic design and memory systems.
• Experience with RTL simulation, debugging, and synthesis processes.

Skills

• Strong analytical and problem-solving skills.
• Ability to independently design and debug complex ASIC functional blocks.
• Familiarity with clock-domain crossing (CDC) and reset design.
• Experience working with verification engineers to resolve functional issues.