Palo Alto Networks is seeking an experienced ASIC design lead for our ASIC team. You will own module design from specification through silicon bring-up, collaborating with verification and physical-design to meet aggressive performance, power, and schedule goals.
The role requires 10+ years of front-end ASIC design ownership, expert SystemVerilog RTL skills, and strong scripting abilities. Networking or cybersecurity domain knowledge is a plus.
#J-18808-LjbffrSenior ASIC Design Architect—AI-Driven Verification in ca at Unknown Company
This position is listed as full time and onsite.