NVIDIA is seeking a Senior ASIC Design Engineer for Clocks IP (Finance) to architect clock domains, collaborate with GPU/CPU teams, and optimize PPA across DFx and timing closure. You will contribute to RTL clocking implementations and work with physical design, timing, and verification teams to bring up silicon.
The role emphasizes end-to-end ASIC delivery, interaction with multiple groups, and strong Verilog/Python skills.
#J-18808-Ljbffr