Senior ASIC Cache Controller Engineer - High-Performance SoC

Apple Inc. in Santa Clara, CA, is seeking an experienced hardware design engineer to build the cache subsystem for a high-performance System on a Chip (SoC). The role involves RTL design, micro-architecture development, and performance/power/area trade-off analysis in line with architectural guidelines.

The candidate will collaborate on front-end netlist, timing closure with the physical design team, and contribute to shaping memory hierarchy to meet demanding latency and bandwidth requirements.