Johns Hopkins Applied Physics Laboratory seeks an experienced Senior Physical Design ASIC Engineer to advance miniature systems for various applications. In this role, you'll manage the digital back-end flow from synthesis to layout and perform essential physical verification.
The successful candidate will have at least 6 years of ASIC design experience, familiarity with Cadence tools, and the ability to obtain a security clearance. Enjoy a generous benefits package and a healthy work/life balance.
#J-18808-LjbffrSenior ASIC Back-End & Physical Layout Engineer in laurel at Unknown Company
This position is listed as full time and onsite.