Senior Analog/Mixed-Signal Verilog Modeling Engineer

Broadcom Inc. in Irvine seeks an experienced DMS model developer to create Digital‑Mixed Signal models for analog IPs using SystemVerilog. You will interface with analog design and DV teams to support verification, and leverage Verilog‑AMS for modeling and Cadence tools for linting and simulation.

The role requires a strong background in RTL/DTL coding, testbench creation, and hands‑on scripting (TCL/Perl/Python) with exposure to AI-assisted modeling approaches.