OVT group in California seeks an experienced engineer to design and optimize column-level ADC circuits for CMOS image sensors, focusing on layout efficiency and performance.
You will collaborate across teams, perform RCX extraction with parasitic analysis, and develop physical design guidelines. A minimum of 6 years in analog/silicon, and an MSEE or equivalent, are required; image sensor readout design experience is a strong plus.
#J-18808-LjbffrSenior Analog Layout Engineer for CMOS Image Sensor ADCs in santa clara at Unknown Company
This position is listed as full time and onsite.