Senior Analog IC Design Lead - High-Speed SerDes

Cadence in California seeks a Principal Analog IC Designer to lead the design and verification of analog/mixed-signal circuit blocks from initial concept/specification through final verification of conformance to customer specifications.

The role requires a minimum of 7 years in CMOS SerDes or high-speed I/O IC design, deep knowledge of jitter and signal equalization, and proficiency with CAD tools for simulation, layout, and verification, including Cadence platforms. Experience at >10Gbps in <28nm nodes is a plus.