Senior Analog Design Architect - DDR I/O & PLL

Renesas is seeking an experienced analog/mixed-signal IC design engineer to architect, verify and optimize CMOS analog blocks for custom ASICs. You will lead DDR I/O interfaces, collaborate with cross-functional teams, and mentor junior engineers while improving power, area and reliability.

The role requires a strong background in high-speed DDR interfaces, signal integrity, and hands-on use of Cadence tools for rigorous verification and validation processes.