Samsung Semiconductor, Inc. is seeking a talented Senior/Staff PLL Designer to develop high‑performance PLL and clocking subsystems for RF transceivers, SerDes, and high‑speed I/O.
You will design and verify frequency synthesizers and clock generation circuitry in advanced CMOS tech. The role requires extensive hands‑on experience with VCOs, DCOs, phase detectors, and related circuitry, plus strong CAD tool proficiency and layout skills.
#J-18808-LjbffrSenior Analog & Mixed-Signal PLL Designer in san jose at Unknown Company
This position is listed as full time and onsite.