Silicon Brite Technologies Inc. seeks an experienced layout engineer to perform analog and mixed-signal IC layout using Cadence Virtuoso. The role covers design of chip layouts, verification and parasitic extraction for AMS circuits, from blocks to full-chip level.
The ideal candidate has a BS in EE, 15+ years in semiconductors, and strong Cadence tool knowledge. Remote work is available globally, with base in San Jose, CA preferred.
#J-18808-LjbffrSenior AMS IC Layout Engineer — Remote in san jose at Unknown Company
This position is listed as full time and able to be worked remotely.