Senior AI SoC Design Engineer: RTL, Power & Performance

Jobtailor seeks an experienced RTL design engineer to contribute to complex SoC developments, integrating IP blocks and subsystems into full chip designs. The role involves architecture definition, quality checks, and close collaboration with verification teams to ensure robust RTL and timing converge.

The ideal candidate has 7+ years in RTL for ASIC/SoC, deep knowledge of bus protocols like AXI/AHB, and strong scripting skills (Python/TCL) for design automation.