Samsung Semiconductor Inc in San Jose seeks a Senior Physical Design AI/ML Engineer for the Logic Pathfinding Lab. You will apply AI/ML to improve design simulation accuracy and throughput, and contribute to DTCO knob optimization for sub-2nm nodes.
The role requires a PhD with hands-on RTL synthesis, place & route, PDK generation, and collaboration across teams. Strong Python/C++ and ML frameworks are essential, with onsite presence in San Jose.
#J-18808-LjbffrSenior AI/ML Engineer for Chip Layout Optimization in san jose at Unknown Company
This position is listed as full time and onsite.