Astera Labs in San Jose seeks a Senior Software Engineer for AI-enabled RTL design and formal verification. You will design and deploy AI applications, build LLM-powered tooling, and integrate agentic workflows with CAD/EDA flows.
The role blends ASIC software engineering with RTL/verification expertise and hands-on work across Verilog/SystemVerilog and AI pipelines. You will collaborate with RTL design, DV, formal verification and CAD teams to accelerate design closure and improve lint/formal
#J-18808-LjbffrSenior AI Engineer for RTL Design & Formal Verification in san jose at Unknown Company
This position is listed as full time and onsite.