RTL-to-PD Engineer for Next-Gen AI Hardware

A cutting-edge AI hardware firm located in San Jose is seeking an RTL to PD Engineer to enhance their next-generation AI silicon designs. This role involves managing handoffs, driving timing closure, and developing automated design flows using advanced tools. Ideal candidates should have over 3 years of relevant experience and proficiency in SystemVerilog/Verilog with a solid understanding of Cadence and Synopsys tools. Competitive salary and a flexible PTO policy are offered to attract innovative thinkers.
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