A cutting-edge AI infrastructure company is seeking an experienced RTL to PD Engineer to own design handoffs and ensure high-quality implementations in the development of next-generation AI silicon. Applicants should have over 3 years of experience in RTL-to-PD processes, proficiency in SystemVerilog, and familiarity with Cadence and Synopsys tools. The role offers competitive compensation, flexible PTO, and a collaborative environment focused on innovation.
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RTL-to-PD Design Engineer for AI Hardware — Flexible PTO in san jose at Unknown Company
This position is listed as full time and onsite.