RTL/PD Design Engineer for Tapeout-Ready ASICs

Normal Computing seeks an RTL and PD Design Engineer to own RTL from microarchitecture to tapeout, delivering GDSII-ready designs. You will write SystemVerilog, collaborate with architecture, verification, and fab teams, and guide designs through synthesis, place-and-route, CTS, timing, LVS/DRC, and tapeout.

Strong candidates have multiple tapeouts, hands-on production RTL in SystemVerilog, and the ability to shape architecture when specifications are still evolving.