RTL Design Engineer – Security IP & SoC Subsystems

AMD in Austin, TX is seeking an RTL IP Design Engineer to join the Security IP (SECIP) Design team. You will contribute to block-level RTL design for embedded MP subsystems and hardware accelerators across AMD SoC platforms.

Collaborate with architecture to define specs, drive RTL development, and meet performance, power, and area targets. The role requires strong Verilog/SystemVerilog skills, scripting, and hands-on experience with verification methodologies, C-DPI, and SoC integration.