RTL Design Engineer - Next-Gen Mixed-Signal ASICs

Teradyne in North Reading, MA, seeks an experienced RTL Designer to join the Silicon Technology Engineering group. You will contribute to advanced node ASIC development, collaborating with Analog and architecture teams across specification, design, verification, physical design, and silicon bring-up.

The role emphasizes high-speed memory, timing closure, and automation via scripting. Minimum 5+ years in EE with Verilog RTL, CDC/STA, and memory/serial interfaces; strong collaboration with